OR gate from 2:1 MUX: Assumptions: 's' is the select line for the mux. 'I0 and I1' be the input data lines of the mux. 'Z' be the ouput of the Mux.
a,b inputs of the OR gate.
method : Connect the input b to the select line 's' of mux. Connect input 'a' to the 'I0' line input of mux. Connect the 'I1' line input of mux to LOGIC 1(VCC). Now ur mux out 'z' will be "a or b"
Make either of input A or B as select line of MUX, connect the other input to 0th input line. 1st input of the MUX is always tied to logic 1.
ReplyDeleteOR gate from 2:1 MUX:
ReplyDeleteAssumptions:
's' is the select line for the mux.
'I0 and I1' be the input data lines of the mux.
'Z' be the ouput of the Mux.
a,b inputs of the OR gate.
method :
Connect the input b to the select line 's' of mux.
Connect input 'a' to the 'I0' line input of mux.
Connect the 'I1' line input of mux to LOGIC 1(VCC).
Now ur mux out 'z' will be "a or b"
in 2:1 mux there will be 2 inputs...give '0' to one i/p (say i1)and '1' to another....(say i2)
ReplyDeletegive the same (i2 =1)i/p to selection line...
In order to design an OR gate with 2*1 MUX, one of the inputs of the MUX would be the selection line and the other would be HIGH.
ReplyDeletefor a 2 X 1 MUX give ur select line as input A
ReplyDelete1st input line as logic 1
2nd input line as B input
u will get or gate output